Circuits which combine bipolar and complementary metal-oxide semiconductor (CMOS) devices on the same silicon substrate are known as BiCMOS circuits. BiCMOS logic circuits share the advantages of both CMOS and bipolar circuitries. For example, BiCMOS circuits are characterized by extremely low quiescent power consumption, rail-to-rail output capability, high-density and high input impedance. At the same time, the bipolar elements provide very fast switching capabilities and feature good performance over temperature and power supply variations.
Emitter-coupled logic (ECL) is a popular family of bipolar logic circuitry which is found extensively in the prior art. Lately, researchers have attempted to create low cost BiCMOS ECL logic gates in order to take advantage of the faster bipolar logic switching capabilities while minimizing the quiescent power consumption by utilizing CMOS circuit devices. Whereas ECL processes can fabricate resistors for ECL circuits, BiCMOS processes typically do not include a resistor device, and must utilize CMOS devices instead. For example, U.S. Pat. No. 5,124,580 describes a BiCMOS logic circuit which includes an emitter-coupled pair of bipolar transistors connected to differentially compare an input signal with a reference potential. Each of the transistors is loaded by a p-channel MOS (PMOS) transistor operated in its linear region.
One of the drawbacks of prior art BiCMOS ECL logic circuits has been the inability to provide an appropriate reference circuit which maintains the PMOS load transistors in a linear region despite variations in current, temperature, process etc. Often, the difficulty lies in having the PMOS load devices track with the n-channel MOS (NMOS) devices which are typically used as current sources. Another problem has been the use of large voltage swings, sometimes as large as the power supply voltage, for switching between the logic voltage levels. Most crucial is the fact that large voltage swings add delay to the circuit, thereby diminishing performance. One of the advantages of ECL is that it uses small voltage swings. The large (power supply voltage) swings used in CMOS circuits add delay to the circuit, thereby diminishing performance. These large swings also generate more noise.
Yet another related problem occurs when the input voltage exceeds the output swing. This typically causes saturation of the input bipolar transistors, which also slows the device's speed considerably. At the other extreme, if the voltage swing is too small there can be a problem in maintaining a sufficient noise margin. Of course, all of the aforementioned problems are exacerbated by variations in temperature, voltage, and processing.
As will be seen, the present invention provides a reference circuit in conjunction with a BiCMOS ECL gate that allows the use of controlled, small voltage swings, and emitter-following to increase the speed of the logic gate.